1. Field of the Invention
The present invention relates to semiconductor switching of radio frequency (RF) signals, and in particular to targeted cancellation of harmonics of a fundamental operating frequency (Fo) of an RF signal.
2. Description of Related Art
Radio frequency (RF) switches and power amplifiers are important building blocks in wireless communication systems, and are found in most common transceivers, such as cellular telephones. RF switch performance is gauged according to several operating parameters, including: insertion loss, switch isolation, the “1 dB compression point,” and switching speed. Optimizing these parameters is a primary design goal of any RF switch design. However, because an RF switch is often coupled directly to a transmitting antenna, another important performance criterion is the ability of an RF switch to avoid generating unwanted harmonic content.
FIG. 1a is a simplified schematic diagram of a typical single-pole, single-throw (SPST) RF switch 10, including input clamping. An input node 1 is coupled to a source, such as the output from a power amplifier in the transmitter section of a transceiver. The source is represented as a sinusoidal signal source in series with equivalent impedance R0 9, which, ideally, is perfectly resistive. When biased “on,” a switch M1 5 couples the source signal to an output node 3. The output node 3 is typically coupled to an antenna. M1 5 is biased “on” by providing an appropriate voltage at the DC ON control node of R1, the other side of which is coupled to the gate of M1 5. When M1 is off, a switch M2 7 is typically turned on to clamp the input to a common voltage. Such clamping reduces pass-through of signals between the unused input node 1 and the output node 3 due to incidental conduction on M1 5. As such, appropriate “off” biasing must be concurrently provided to the DC OFF node of resistor R2 to turn off the clamping switch MOSFET M2 7. Conversely, when M1 is biased on and M2 is biased off, the source at node 1 is coupled to the output node 3. The output node 3 is coupled in turn to a load 11. The load 11 is represented in FIG. 1 by resistor RO1, but in practice is typically an antenna, to which the output node 3 is coupled via a transmission line.
FIG. 1b is a simplified schematic of the circuit of FIG. 1a, further illustrating some details of parasitic element equivalent circuits. When properly biased “off,” M1 has almost infinite resistance from drain to source through its channel. However, there is a finite capacitance Cds1 19 from drain to source. Cds1 19 may be significantly due to a series combination of the “off” gate capacitances to drain and to source, Cgd off 15 and Cgs off 17, respectively. M2, which is properly biased “on,” also includes a parasitic drain-source capacitance Cds, but it Cds has little effect due to the low on resistance of the channel, represented as r1, that parallels it. However, the “on” gate capacitances to drain and source, Cgd on and Cgs on, continue to provide a conduction path between the channel and the gate resistor R2.
FIG. 2 is a simplified schematic diagram illustrating a single pole double throw (SPDT) switch, fabricated by combining two SPST switches such as shown in FIG. 1. The SPDT switch of FIG. 2 has an RF common connection 25, which is typically coupled to an antenna via a transmission line. In a first state, the RF common 25 may be coupled to RF1 21 via a FET 23 that is biased “on.”) In this state a FET 28 is also biased “on,” while FET 24 and 27 are biased “off.” In an alternative second state, RF common 25 may be coupled to RF2 22. In this second state, FETs 24 and 27 are biased “on,” while FETs 23 and 28 are biased “off.” Just two drive signals are needed to switch the elements between the first and second states: SW and its inverse, SW_. When SW is “on” or true, SW_ is “off” or false, and vice versa.
RF switches have heretofore been implemented in various component technologies, including bulk complementary-metal-oxide-semiconductor (CMOS) and gallium-arsenide (GaAs) technologies. Indeed, most high performance high-frequency prior art switches use GaAs technology. Prior art RF switch implementations have attempted to improve the RF switch performance with mixed results, and with varying degrees of integrated circuit complexity and yield. For example, bulk CMOS RF switches disadvantageously exhibit high insertion loss, low compression, and poor linearity performance characteristics. In contrast, due to the semi-insulating nature of GaAs material, parasitic substrate resistances can be greatly reduced using these materials, thereby reducing RF switch insertion loss. Similarly, the semi-insulating GaAs substrate improves switch isolation.
Although GaAs RF switch implementations offer good performance characteristics, the technology has several disadvantages. For example, GaAs technology exhibits relatively low yields of properly functioning integrated circuits. GaAs RF switches tend to be relatively expensive to design and manufacture. In addition, although GaAs switches exhibit good insertion loss characteristics as described above, they may have low-frequency limitations due to slow states that are present in the GaAs substrate. The technology also does not lend itself to high levels of integration. Consequently, complex digital control circuitry associated with GaAs RF switches must be implemented “off chip” from the switch. Even the low power control circuitry associated with the switch has proven difficult to integrate. This is disadvantageous because it increases the overall system cost for manufacturing circuits of a given size and complexity, as well as reducing system throughput speeds.
Moreover, GaAs designs and methodologies, which typically employ non-insulating, junction-based FETs, are often incompatible with technologies that employ insulating gate FETs, such as CMOS. Though the same schematic symbols are often used for both types of FETs (GaAs MESFETs and MOSFETs in, e.g., silicon), they do not behave similarly. GaAs circuits often rely upon conduction through forward-biased gate junctions to properly bias a circuit. Consequent to this and other distinctions, one cannot presume that substituting CMOS devices according to a GaAs design will result in a circuit that will function as intended, or indeed will function at all.
Devices that use semiconductor RF signal switching circuits, such as cellular telephones, operate in crowded RF spectrums, and are stringently regulated in regard to spurious emissions. Because failure to comply with regulatory limits can make an entire device unmarketable, it is crucial that the component RF signal switching circuits in such devices avoid contributing harmonic power that could cause such a failure. Unfortunately, semiconductor devices in such switches are never “ideal.” Some non-ideal characteristics will inevitably introduce distortion into the signal being transmitted, inducing unwanted signal content at harmonics of the fundamental transmission operating frequency, Fo. The amount of distortion, as well as the resultant magnitude of the resulting harmonic signals, is often a function of the amplitude or power of the output signal. Accordingly, such harmonic distortion may restrict the power handling capability of the switch.
In addition to enabling fabrication of an integrated RF signal switching circuit having improved performance characteristics in terms of insertion loss, isolation, and compression, it is also desirable to enable fabrication of an RF switch having reduced levels of harmonic content. Methods and circuits are therefore set forth herein that may enhance performance, and are in particular suitable for reducing the harmonic content of an RF signal conducted by a semiconductor RF switch circuit.